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Integrating MEMS and ICs

Andreas C. Fischer, Fredrik Forsberg, Martin Lapisa, Simon J. Bleiker, Göran Stemme, Niclas Roxhed, Frank Niklaus

Microsystems & Nanoengineering 1, Article number: 15005 (2015)



The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than-Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

Fig.1 MEMS and IC integration methods are based on either (a) hybrid multi-chip solutions (described in Section 2) or (b) system-on-chip solutions (described in Section 3).

Fig.2 (a) 2D side-by-side integration with flip-chip and wire bonded interconnections. (b) Photograph of a decapsulated Colyibrys MS9000-series accelerometer (Colibrys Ltd, Yverdon-les-Bains, Switzerland). ASIC and passive chips are placed side-by-side with an encapsulated MEMS chip. All chips have wire bonded interconnections. Package dimensions: 8.9 × 8.9 × 3.2 mm3.

Fig.3 (a) System-in-package solution constructed via 3D stacking with wire bonded interconnects. (b) SEM image of a decapsulated STMicroelectronics LIS331DLH 3-axis accelerometer (STMicroelectronics, Geneva, Switzerland). An ASIC chip is stacked on an encapsulated MEMS chip and interconnected via wire bonds. Package dimensions: 3 × 3 × 1 mm3. From Ref 54.

Fig.4 (a) Chip-scale package (CSP): the MEMS and IC chips are attached via face-to-face flip-chip bonding. (b) Photograph of a 3-axis accelerometer (VTI, CMA 3000) fabricated using chip-on-MEMS technology. Package dimensions: 2 × 2 × 1 mm3. From Ref 61.

Fig.5 (a) Sketch of a 3D sensor node stack fabricated using through-silicon vias. (b) Photograph of a 3D sensor node stack fabricated using through-silicon vias at the wafer level. From Ref 62.

Fig.6 (a–c) Advanced porous silicon membrane (APSM) process developed by Bosch. (a) n+ and p+ implantation. (b) Anodic HF etching. (c) Sintering to form a cavity and a silicon epitaxial layer. Adapted from Ref 65 and Ref 66. (d–e) Similar MEMS-first platform developed by SiTime (now MegaChips, Japan) and Stanford University. MEMS structures are fabricated in the SOI device layer and released by means of HF vapor etching. The ICs are fabricated in the epitaxially grown silicon top layer. (d) Schematic cross-section. (e) SEM image of a fabricated resonator72.

Fig.7 Processing sequence for the ‘plug-up’ concept. (a) Small holes are etched, and a thin HF-permeable poly-silicon layer is deposited. (b) The buried oxide is etched with HF. (c) The holes are closed via the deposition of poly-silicon. (d) CMP followed by CMOS processing. Adapted from Ref 73.

Fig.8 Multilevel MEMS formed within a shallow trench using the Sandia National Laboratories M3EMS platform. From Ref 76.

Fig.9 (a) Process outline for the Mod-MEMS platform. From Ref 77. (b) Schematic cross section and photograph of an SOI-MEMS device, showing the released MEMS structure fabricated from an SOI wafer, the isolation trench, and the IC area. Adapted from Ref 6 and Ref 80.

Fig.10 Various approaches to monolithic MEMS and IC integration using MEMS-last processing via the bulk micromachining of the IC substrate: (a) Front-side wet etching. (b) Backside wet etching. (c) Backside wet etching using an electrochemical etch stop. (d) Front-side dry etching using a metal hard CMOS mask. (e) Front-side dry etching using a photoresist mask. (f) Front-and backside anisotropic deep-reactive ion etching (DRIE) of a CMOS wafer. Adapted from Ref 98.

Fig.11 Fabrication process and images of an IC-integrated MEMS microphone. Adapted from Ref 6 and Ref 113.

Fig.12 Typical processing scheme for monolithic MEMS-on-IC integration using MEMS-last processing via the deposition and surface micromachining of two layers: (a) Manufacturing of the CMOS wafer. (b) Deposition and patterning of the sacrificial layer. (c–d) Deposition and patterning of the first layer of MEMS material, the second sacrificial layer and the second layer of MEMS material. (e) Etching of the sacrificial layer. (f) Schematic diagram of a deflected torsional micro-mirror pixel. (g) SEM images of micro-mirror pixels with the mirror plate of the center pixel removed to expose the underlying hinge structures. (h) Packaged DLPTM chip containing an array of more than two million micro-mirrors, placed in a ceramic package with a glass window6.

Fig.13 Via-first heterogeneous integration platform from InvenSense Inc., San Jose, CA, USA, which is used for, e.g. the high-volume manufacturing of gyroscope products: (a) A pre-fabricated monocrystalline silicon MEMS sensor, including a cap, is (b) bonded to a pre-fabricated CMOS-based IC wafer containing etched cavities; then, (c) the contact pads on the CMOS wafer are revealed. (d) SEM images of a gyroscope integrated with CMOS circuits. From Ref 9.

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